Complicated digital integrated circuits, such as FPGAs, microprocessors, application-specific integrated circuits (ASICs), or the like (generally, chips), have a large number of output buffers for driving output signals off-chip. The output buffers generally change state in unison, which causes large currents with fast times (high dI/dt) to flow in the power supply and ground buses on the chip. Because of the self-inductance of the buses, the fast current flows result in voltage transients on the power supply and ground buses. The transients on the power supply bus and the ground bus are generally referred to as power supply droop and ground bounce, respectively. If the voltage transients are significant enough, the chip may intermittently fail. a common technique to reduce the voltage transients is to slow down the switching speed of each output buffer by limiting the drive current to the output transistors of each buffer, thereby slowing the rate that the transistors switch from turned-off to fully turned-on. However, this technique significantly complicates the output buffer circuitry and might sufficiently weaken the buffer during output signal transitions such that the output signals from the buffer becomes unacceptably susceptible to crosstalk from other near-by signals.